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Testing Resource Isolation for System-on-Chip Architectures

Year: 2024

Type: article

Abstract: Ensuring resource isolation at the hardware level is a crucial step towards more security inside the Internet of Things. Even though there is still no generally accepted technique to generate appropriate tests, it became clear that tests should be generated at the system level. In this paper, we illustrate the modeling aspects in test generation for resource isolation, namely modeling the behavior and expressing the intended test scenario. We present both aspects using the industrial standard PSS and an academic approach based on conformance testing.

Source: Electronic Proceedings in Theoretical Computer Science

DOI: 10.4204/eptcs.399.7

Authors: Philippe Ledent, Radu Mateescu, Wendelin Serwe

Institutions: Institut polytechnique de Grenoble, Centre National de la Recherche Scientifique, Institut national de recherche en sciences et technologies du numérique, Laboratoire d'Informatique de Grenoble, Université Grenoble Alpes

Language: English

Topic: Software Testing and Debugging Techniques

Subfield: Software

Field: Computer Science

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: diamond

OpenAlex ID: W4393201671