Work

Impact of Using Off-Chip Memories on Reliability of Edge Computing Systems to Single-Event Upsets

Year: 2024

Type: conference-paper

Abstract: This work investigated the impact of using either an off-chip or an on-chip non-volatile memory on the reliability of two different RISC-V (reduced instruction set computer V) based edge computing systems operating under 14-MeV neutrons. Radiation testing results suggest the single-event upset (SEU)-induced failure rate of the case-study system with off-chip memory would be around 2.5 times higher than its counterpart with on-chip memory. Additional results of classical RISC based edge computing system running neural networks are also reported.

Source: European Conference on Radiation and Its Effects on Components and Systems

DOI: 10.1109/radecs61970.2024.11298594

Authors: Luiz Henrique Laurini, Leonardo Alexandrino de Melo, Alberto Bosio, Rodrigo Possamai Bastos

Institutions: Institut polytechnique de Grenoble, Centre National de la Recherche Scientifique, Techniques of Informatics and Microelectronics for Integrated Systems Architecture, Institut des Nanotechnologies de Lyon, Lyon 1 Université, École Centrale de Lyon, Institut National des Sciences Appliquées de Lyon

Language: English

Topic: Radiation Effects in Electronics

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: green

OpenAlex ID: W4399793760

FWCI:

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