Year: 2024
Type: article
Abstract: Turbo product codes (TPCs) have been widely used for bit error correction in high‐speed applications such as data storage. This letter introduces an efficient hard‐input hard‐output iterating TPC decoder module. A transpose memory utilizing static random access memory (SRAM) is integrated into the decoder to achieve a low hardware overhead. The transpose memory, based on an 8T SRAM bit‐cell, supports both horizontal (row‐wise), and vertical (column‐wise) read/write operations. It is prototyped under a 28nm high‐k/metal gate stack process with bit‐cell size of 0.582 µm 2 . This specialized SRAM significantly reduces the hardware overhead when compared with a register‐array‐based transpose memory without significant throughput loss. A field programmable gate array (FPGA) evaluation platform is utilized to emulate the TPC decoder module, and the maximum decoder throughput is up to 6.49 Gbps at 250 MHz.
Source: Electronics Letters
DOI: 10.1049/ell2.13296
Authors: Jianjun Luo, Xiaoyu Xu, Yifan Shen, Boming Huang, Wenkui Wang
Institution: Hangzhou Dianzi University
Language: English
Subfield: Computer Networks and Communications
Field: Computer Science
Domain: Physical Sciences
Open Access status: gold
Estimated APC paid: $2,540
Award: G3642759932
OpenAlex ID: W4401428908