Work

Two-level Stacked Nanowire MOSFETs: A Low Temperature Analysis of the Low-Field Mobility Degradation Factors

Year: 2024

Type: article

Abstract: This study explores the carrier mobility and its degradation factors in relation to temperature for 2-level stacked nanowire MOSFETs within the temperature range of 100 K to 400 K. The low-field carrier mobility and its degradation factors were extracted using the Y-function. Additionally, it was observed that the peak transconductance is achieved at a higher overdrive voltage (VG-VTH), particularly as the temperature decreases. Notably, the low-field mobility is more sensitive in wider devices. Compared to other technologies such as omega-gate nanowires and planar fully depleted SOI transistors, this technology exhibits less sensitivity of low-field mobility to temperature variations. The first-order degradation factor was observed to decrease with rising temperature, while the second-order factor exhibited an increase within the same temperature range. The variation in the first and second order degradation factors with temperature is more pronounced in wider devices.

Source: Journal of Integrated Circuits and Systems

DOI: 10.29292/jics.v19i2.816

Authors: Jaime Calçade Rodrigues, Mikael Cassé, Sylvain Barraud, Maud Vinet, Olivier Faynot, Marcelo Antonio Pavanello

Institutions: Centro Universitário FEI, Commissariat à l'Énergie Atomique et aux Énergies Alternatives, Laboratoire d'Électronique des Technologies de l'Information, Université Grenoble Alpes

Language: English

Topic: Advancements in Semiconductor Devices and Circuit Design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: diamond

Funders: Fundação de Amparo à Pesquisa do Estado de São Paulo, Coordenação de Aperfeiçoamento de Pessoal de Nível Superior, Conselho Nacional de Desenvolvimento Científico e Tecnológico

Awards: G29316538, G295657101, G4208080346, Atomistic simulation of nanowire MOSFETs electrical properties