Year: 2024
Type: conference-paper
Abstract: With the rise of AI, computing hardware with varying architectures has emerged. For some frequently used AI kernels, these hardwares provide special accelerators and related instructions. For example, since the Volta architecture, Nvidia GPUs have provided tensor cores to optimize operations related to matrix multiplication. The vector extension of the RISC-V architecture provides instruction-level parallelism for kernels.
Authors: Zi-Xuan Chen, Wuu Yang
Institution: National Yang Ming Chiao Tung University
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: gold
Award: G4213487846
OpenAlex ID: W4401454477
