Work

Hybrid ALM-DSP TDC in Intel Arria 10 FPGA

Year: 2024

Type: article

Abstract: The article presents the first implementation of a time-to-digital converter (TDC) using a digital signal processing (DSP) block from an Intel FPGA. The design and configuration capabilities of the DSP blocks of the leading FPGA manufacturers, AMD and Intel, are compared in the context of time/digital conversion. Next, three variants of TDC converters are presented. The problem of ultra-wide bins observed in both the classic version of the converter based on the Adaptive Logic Modules (ALM) and the version built using only DSP blocks has been mitigated in a hybrid variant, combining both solutions. The proposed variant of the hybrid ALM-DSP TDC implemented in Arria 10 FPGA from Intel (20 nm process node) achieved a resolution of 2.1 ps, a single-shot-precision better than 6.36 ps and reduced the maximum differential nonlinearity (DNL) error from 74.5 ps to 12.7 ps, while maintaining relatively low use of logical resources and design complexity.

Source: Measurement

DOI: 10.1016/j.measurement.2024.115523

Authors: Mariusz Mścichowski, Paweł Kwiatkowski

Institution: Military University of Technology in Warsaw

Language: English

Topic: Advancements in PLL and VCO Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: hybrid

Estimated APC paid: $3,650

Funders: Ministerstwo Edukacji i Nauki, American Institute of Polish Culture