Work

Graceful Register Clustering and Rebanking for Power and Timing Balancing

Year: 2024

Type: article

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI: 10.1109/tcad.2024.3448233

Authors: Yi-Ting Hsieh, Tung-Wei Lin, Ya-Chu Chang, Hao-Yu Wu, Iris Hui-Ru Jiang

Institutions: University of California, Berkeley, National Taiwan University

Language: English

Topic: VLSI and FPGA Design Techniques

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

Funder: National Science and Technology Council

OpenAlex ID: W4401750081

FWCI:

Cites: 19

Cited by:

Related to: 10