Work

Venus Surface Environmental Chamber Test of SiC JFET-R Multi-Chip Circuit Board

Year: 2024

Type: article

Abstract: This paper describes a first attempt to build and operate a multi-chip prototype lander control and sensor signal digitization electronics circuit board comprised of ten NASA Glenn IC Generation 11 SiC JFET-R IC chips in 460 °C, 9.4 MPa harsh Venus surface conditions. The lander circuit ceased electrical operation prematurely at 107 °C as the Venus chamber heated up. Microscopic post-test inspections indicate that only one of the ten SiC chips on the board failed. Most of circuit-damaging cracks observed on the failed chip corresponded to micron-scale irregularly-shaped dielectric film hillock defects. The study of these defects suggests minor processing changes to eliminate this suspected root failure cause.

Source: Diffusion and defect data, solid state data. Part B, Solid state phenomena/Solid state phenomena

DOI: 10.4028/p-u3mieo