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A Fast Three-Layer One-Side Bottleneck Channel Routing with Layout Constraints Using ILP

Year: 2024

Type: article

Abstract: An algorithm for three-layer bottleneck channel routing problem that uses ILP is proposed. The proposed algorithm determines the track and layer assignment of nets for problems with layout constraints in which pins of each net are placed on the upper boundary of the adjacent regions on both sides of the bottleneck channel. The proposed algorithm restricts the routing pattern of each net to one of three patterns by taking feasibility into account, and outputs a solution in a few seconds when the number of nets is 300.

Source: IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences

DOI: 10.1587/transfun.2024vlp0002

Authors: Kazuya TANIGUCHI, Satoshi TAYU, Atsushi TAKAHASHI, Mathieu MOLONGO, Makoto MINAMI, Katsuya NISHIOKA

Institution: Tokyo Institute of Technology

Language: English

Topic: VLSI and FPGA Design Techniques

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: bronze

OpenAlex ID: W4402338717

FWCI: 0.729

Cites: 21

Cited by: 7

Related to: 10