A low power all-digital frequency locked loop with resource-efficient frequency detector and hysteresis lock detector
Year: 2024
Type: article
Abstract: Trillions of Internet of Things devices require rigorous design trade-offs regarding size, cost, and energy efficiency, leading to design challenges for clock modules. This paper proposes a low-power all-digital frequency locked loop (ADFLL) featuring a digital frequency detector with minimum D-type flip-flop usage and a lock detector with hysteresis lock/unlock decision zone, suitable for system-on-chip applications. The ADFLL is verified in the field-programmable gate arrays (FPGA) and is implemented as an on-chip clock generator in a radio frequency identification tag using 130nm CMOS technology with 0.185×0.26mm2 size. The generated clock has ±0.25% frequency accuracy with good temperature and process robustness.
Source: IEICE Electronics Express
Authors: Yuxiao Zhao, Jin Mitsugi, Hao Min
Institutions: Fudan University, Keio University
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: diamond
Funder: Keio University
OpenAlex ID: W4402347187