Work

Analysis and Mitigation on Mismatch-Induced Spurious Gate–Source Voltages in SiC Bridge-Leg Power Modules With Kelvin Sources

Year: 2024

Type: article

Source: IEEE Journal of Emerging and Selected Topics in Power Electronics

DOI: 10.1109/jestpe.2024.3456137

Authors: Cheng Zhao, Laili Wang, Junhui Yang, Shijie Wu, Huaiqing Zhang

Institutions: Chongqing University, State Key Laboratory of Electrical Insulation and Power Equipment, Xi'an Jiaotong University

Language: English

Topic: Silicon Carbide Semiconductor Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

Funders: China Postdoctoral Science Foundation, Fundamental Research Funds for the Central Universities

Awards: G129755446, G6030442489

OpenAlex ID: W4402351436

FWCI: 0.103

Cites: 25

Cited by: 1

Related to: 10