Software-Assisted Event Builder for Belle II Experiment
Year: 2024
Type: article
Abstract: In this article, we present the design of the hybrid event builder algorithm for Belle II DAQ. The event builder is implemented in PCIe40 field-programmable gate array (FPGA) boards and reads up to 48 127 MB/s channels per board. The first version of the event builder implemented the algorithm entirely in the firmware of the FPGA. But due to limited onboard memories, there are hard limitations on the operation conditions. The new algorithm uses independent event processing for each channel in FPGA and a highly optimized readout software for final event building. This allowed us to increase the throughput of the system from 600 MB/s to 7.25 GB/s on a readout computer with 20 CPU cores. We successfully use the system to take data at trigger rates of up to 5.5 kHz in run 2 of Belle II experiment since February 2024.
Institutions: High Energy Accelerator Research Organization, University of Hawaiʻi at Mānoa, University of Siegen, Laboratoire de Physique des 2 Infinis Irène Joliot-Curie, Kavli Institute for the Physics and Mathematics of the Universe, The University of Tokyo, Institute of Nuclear Physics, Polish Academy of Sciences, Polish Academy of Sciences, Centre National de la Recherche Scientifique, Institut National de Physique Nucléaire et de Physique des Particules, Shandong University
Language: English
Subfield: Nuclear and High Energy Physics
Field: Physics and Astronomy
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W4402570504