AI-Powered Neural Network Verification: System Verilog Methodologies for Machine Learning in Hardware
Year: 2024
Type: article
Abstract: This research focuses on verifying neural network models using System Verilog, with two primary applications: visual edge detection and neuron behavior modeling. In modern chip design, hardware verification plays a crucial role in ensuring that complex neural models perform as expected. A neuron model based on Hubel and Wiesel’s feed-forward network architecture was proposed and tested using integrator and threshold modules implemented in Verilog. The proposed verification methodology employs self-checking test benches, supported by functional coverage and simulation, for comprehensive validation. The results demonstrate efficient verification with high coverage, paving the way for future advancements in hardware neural networks.
Author: Prashis Raghuwanshi
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: hybrid
OpenAlex ID: W4402660613