Work

Hardware–Algorithm Codesigned Low-Latency and Resource-Efficient OMP Accelerator for DOA Estimation on FPGA

Year: 2024

Type: article

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI: 10.1109/tvlsi.2024.3462467

Authors: Ruichang Jiang, Wenbin Ye

Institution: Shenzhen University

Language: English

Topic: Embedded Systems Design Techniques

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4402891687

FWCI: 3.438

Cites: 40

Cited by: 11

Related to: 10