Year: 2024
Type: article
Abstract: Advanced 2.5D/3D wafer-level fan-out packaging technologies have been studied widely in literature and industry in recent years. Miniaturization, reduction in manufacturing costs, improvement in performance, and lower power consumption using packaging technologies drive increase in interconnect density and pitch scaling. Heterogeneous systems in package used in advanced packaging often include a combination of silicon, epoxy underfill or mold compounds, and organic or inorganic passivation or redistribution layers. This heterogeneity poses challenges with manufacturability, process selection, package architecture, and test vehicle design. The coefficient of thermal expansion mismatch, wafer warpage, and wafer yield are some of the critical process challenges. Delamination of silicon side wall or passivation to epoxy underfill or mold compound, joint fatigue are critical reliability challenges. This article explores various processes and reliability challenges with 3D wafer-level fan-out packaging and provides package design and architecture guidelines to overcome these failure modes. Stacked die-to-wafer test vehicles have been used for data collection. Different assembly materials, processes, and tooling have been evaluated to define comprehensive design rules.
DOI: 10.4071/001c.124087
Institution: Intel (United States)
Language: English
Topic: 3D IC and TSV technologies
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: diamond
OpenAlex ID: W4402980988