Work

Schottky barrier memory based on heterojunction bandgap engineering for high-density and low-power retention

Year: 2024

Type: article

Abstract: Dynamic random-access memory (DRAM) has been scaled down to meet high-density, high-speed, and low-power memory requirements. However, conventional DRAM has limitations in achieving memory reliability, especially sufficient capacitance to distinguish memory states. While there have been attempts to enhance capacitor technology, these solutions increase manufacturing cost and complexity. Here, we propose a novel Schottky barrier memory (SBRAM) featuring a heterojunction based on bandgap engineering. SBRAM can be configured as vertical cross-point arrays, which enables high-density integration with a 4F2 footprint. In particular, the Schottky junction significantly reduces the reverse leakage current, preventing sneak current paths that cause leakage currents and readout errors during array operation. Moreover, the heterojunction physically divides the storage region into two regions, resulting in three distinct resistive states and inducing a gradual current slope to ensure sufficient holding margin. These states are determined by the holding voltage (Vhold) applied to the programmed device. When the Vhold is 1.1 V, the programmed state can be maintained with an exceptionally low current of 35.7 fA without a refresh operation.

Source: Discover Nano

DOI: 10.1186/s11671-024-04106-5

Authors: Hyangwoo Kim, Yijoon Kim, Kyounghwan Oh, Ju Hong Park, Chang-Ki Baek

Institution: Pohang University of Science and Technology

Language: English

Topic: Advanced Memory and Neural Computing

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: gold

Estimated APC paid: $1,990

Funders: IC Design Education Center, Ministry of Science and ICT, South Korea, Institute for Information and Communications Technology Promotion