Work

A 2.08-mW 64.4-dB SNDR 400-MS/s Pipelined- SAR ADC Using Mismatch and PVT Variation Tolerant Dynamically Biased Ring Amplifier in 8 nm

Year: 2024

Type: article

Source: IEEE Journal of Solid-State Circuits

DOI: 10.1109/jssc.2024.3471915

Authors: Yong Lim, Jaehoon Lee, Jongmi Lee, Kwangmin Lim, Seunghyun Oh, Jongwoo Lee

Institutions: Samsung (South Korea), Samsung Electronics (South Korea)

Language: English

Topic: Analog and Mixed-Signal Circuit Design

Subfield: Biomedical Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4403277014

FWCI: 1.151

Cites: 62

Cited by: 11

Related to: 10