Work

A Better Kyber Butterfly for FPGAs

Year: 2024

Type: conference-paper

Abstract: Kyber was selected by NIST as a Post-Quantum Cryptography Key Encapsulation Mechanism standard. This means that the industry now needs to transition and adopt these new standards. One of the most demanding operations in Kyber is the modular arithmetic, making it a suitable target for optimization. This work offers a novel modular reduction design with the lowest area on Xilinx FPGA platforms. This novel design, through K-reduction and LUT-based reduction, utilizes 49 LUTs and 1 DSP as opposed to Xing and Li’s [XL21] 2021 CHES design requiring 90 LUTs and 1 DSP for one modular multiplication. Our design is the smallest modular multiplier reported as of today.

Source: International Conference on Field Programmable Logic and Applications (FPL)

DOI: 10.1109/fpl64840.2024.00032

Authors: Jonas Bertels, Quinten Norga, Ingrid Verbauwhede

Institution: KU Leuven

Language: English

Topic: Cryptography and Residue Arithmetic

Subfield: Information Systems

Field: Computer Science

Domain: Physical Sciences

Open Access status: green

Funders: European Commission, Vlaamse regering, Defense Advanced Research Projects Agency

Awards: G2515541506, G3703936846