Work

Rethinking Page Table Structure for Fast Address Translation in GPUs: A Fixed-Size Hashed Page Table

Year: 2024

Type: conference-paper

Abstract: GPU memory virtualization has become essential for efficient programming, memory management, and address space sharing among computing devices in heterogeneous systems. Conventional GPU virtual memory systems use multi-level Radix Page Tables (RPTs) to store virtual-to-physical address mapping in device (GPU) memory. When a TLB miss occurs, a page table walker accesses each level of the page table sequentially to find the desired mapping. These sequential accesses significantly degrade performance, adding pressure to the GPU memory hierarchy. To make matters worse, recent computing systems now support five-level RPTs, further increasing the number of memory accesses required per page table walk.

Source: International Conference on Parallel Architectures and Compilation Techniques

DOI: 10.1145/3656019.3676900

Authors: Sungbin Jang, Junhyeok Park, Osang Kwon, Yongho Lee, Seokin Hong

Institution: Sungkyunkwan University

Language: English

Topic: Parallel Computing and Optimization Techniques

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

Open Access status: hybrid

OpenAlex ID: W4403334641

FWCI: 1.869

Cites: 34

Cited by: 6

Related to: 10