Accelerate RISC-V Instruction Set Simulation by Tiered JIT Compilation
Year: 2024
Type: conference-paper
Abstract: The rising prominence of the RISC-V instruction set architecture has spurred the development of instruction set simulators (ISS), crucial tools for early-stage architecture evaluation and software development. This paper introduces a practical approach to RISC-V ISS using tiered just-in-time (JIT) compilation, a technique commonly employed in high-level language virtual machines but rarely applied to ISS. Our method incorporates an interpreter for initial execution and profiling, a lightweight tier-1 compiler for moderate enhancements, and an aggressive tier-2 compiler for frequently executed code paths. This balanced approach ensures rapid compilation and detailed refinement, resulting in superior performance across various RISC-V workloads. Addressing prevalent challenges in dynamic binary translation, such as indirect jumps and excessive translation times, our paper presents innovative solutions and provides an extensive impact analysis. By leveraging the tiered JIT compilation strategy, we offer a nuanced approach that optimizes the trade-off between compilation speed and code optimization. This strategy not only enhances the overall performance of the RISC-V ISS but also contributes to the broader field of ISS, potentially influencing future developments in architecture evaluation and software development tools.
Authors: Yen-Fu Chen, Meng-Hung Chen, Ching-Chun Huang, Chia-Heng Tu
Institution: National Cheng Kung University
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: gold
OpenAlex ID: W4403490749