Work

PaRSEC: Scalability, flexibility, and hybrid architecture support for task-based applications in ECP

Year: 2024

Type: article

Abstract: This paper highlights the most significant enhancements made to PaRSEC, a scalable task-based runtime system designed for hybrid machines, during the Exascale Computing Project (ECP). The enhancements focus on expanding the capabilities of PaRSEC to address the evolving landscape of parallel computing. Notable achievements include the integration of support for three major types of accelerators (NVIDIA, AMD, and Intel GPUs), the refinement and increased flexibility of the communication subsystem, and the introduction of new programming interfaces tailored for irregular applications. Additionally, the project resulted in the development of powerful debugging and performance analysis tools aimed at assisting users in understanding and optimizing their applications. We present a comprehensive demonstration of these advancements through a series of benchmarks and applications within ECP and beyond, thereby showcasing the enhanced capabilities of PaRSEC across the diverse architectures within the ECP, providing valuable insights into the runtime system’s adaptability and performance across varied computing environments.

Source: The International Journal of High Performance Computing Applications

DOI: 10.1177/10943420241290520

Authors: Aurelien Bouteiller, Thomas Herault, Qinglei Cao, Joseph Schuchart, George Bosilca

Institutions: University of Tennessee at Knoxville, Saint Louis University, Nvidia (United States)

Language: English

Topic: Parallel Computing and Optimization Techniques

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

Open Access status: green

Funders: U.S. Department of Energy, Office of Science, National Nuclear Security Administration

Awards: G1193633358, G1796307089, G3886122786