Work

A 48-58GHz Frac-N DPLL achieving 137fs integrated jitter and fast locking time below 1μs

Year: 2024

Type: conference-paper

DOI: 10.1109/esserc62670.2024.10719534

Authors: Luigi Grimaldi, Agata Iesurum, Giovanni Boi, Fabio Versolatto, Giovanni Steffan, Fabio Padovan, Heorhii Koltsov, Andrea Bevilacqua, Dmytro Cherniak

Institutions: Infineon Technologies (Austria), University of Padua

Language: English

Topic: Advancements in PLL and VCO Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4403675742

FWCI: 0.806

Cites: 11

Cited by: 1

Related to: 10