Work

Demonstration of Gate-Related Trap Characterization in 4H-SiC MOSFETs Using Gate Stress Leakage Current

Year: 2024

Type: article

Abstract: In this work, we demonstrate an innovative technique to characterize the gate-related traps in 4H-SiC MOSFETs by using the gate voltage stress-induced gate leakage current (GSLC) based on the Bayesian Deconvolution technique. We compare the proposed methodology against several approaches to characterize the trapping time constant, demonstrating that the proposed method is reliable and easy to use. The method described in this article extracts the time constants through positive/negative peaks in the time spectrum, which are then used to calculate the activation energies of the traps responsible for degrading the gate oxide. The versatile nature of the proposed method based on trap characterization from GSLC makes it suitable for a wide range of electronic devices experiencing charge-trapping-related degradation phenomena.

Source: IEEE Journal of the Electron Devices Society

DOI: 10.1109/jeds.2024.3486230

Authors: Shivendra Kumar Singh, Tian-Li Wu, Yogesh Singh Chauhan

Institutions: National Yang Ming Chiao Tung University, Indian Institute of Technology Kanpur

Language: English

Topic: Silicon Carbide Semiconductor Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: gold

Estimated APC paid: $1,350

OpenAlex ID: W4403721569