Work

Method to Determine Quantization-Related Parameters of the Digital-to-Time Converter in a Fractional-N Frequency Synthesizer

Year: 2024

Type: article

Abstract: Digital-to-time converters (DTC’s) used in fractional-N frequency synthesizers attempt to cancel the accumulated quantization error (QE) introduced by the divider controller with a view to recovering the integer-N phase noise (PN) performance. The resolution of the DTC needs to be sufficiently fine to suppress its own QE below the intrinsic integer-N jitter and, at the same time, sufficiently coarse to limit the DTC’s hardware needs. In this manuscript, we propose optimal strategies to determine the effective dynamic range, number of bits, quantization resolution, and unity delay of the DTC to achieve these goals; the additional jitter power introduced by input-dithered quantization methods to eliminate DTC-quantization-induced spurs is also considered. DTCs parameterized following these strategies can come close to realizing the spur-free integer-N PN with minimum hardware. Behavioral simulations confirm our analysis.

Source: IEEE Transactions on Circuits and Systems I Regular Papers

DOI: 10.1109/tcsi.2024.3481904

Authors: Xu Wang, Michael Peter Kennedy

Institution: University College Dublin

Language: English

Topic: Advancements in PLL and VCO Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: hybrid

Estimated APC paid: $2,495

Funder: Science Foundation Ireland