Investigation of the Effectiveness of Cache Compression in Central Processors Using the Base-delta-immediate
Year: 2024
Type: conference-paper
Abstract: This paper presents a design in the SystemVerilog hardware description language implementing a system consisting of a cache memory of 32 KB, cache controller, main RAM, compressor and decompressor. The system uses its own implementation of the Base-Delta-Immediate compression algorithm with the logic of storing, reading and writing compressed data in the cache. The results are obtained in the form of cache hits and compression ratio.
Authors: V.R. Polyakov, M.R. Pastukhov
Institution: Volgograd State Technical University
Language: English
Subfield: Artificial Intelligence
Field: Computer Science
Domain: Physical Sciences
Open Access status: gold
OpenAlex ID: W4403890593