Work

Design of Low Voltage & Power Digital Delay Locked Loop in 65nm CMOS Technology

Year: 2024

Type: conference-paper

Source: International Conference on Applied Electronics

DOI: 10.1109/ae61743.2024.10710202

Authors: Kashif Nisar, Hasnain Ahmad, M. Kamran Bhatti, Babar Ali, Zargham H. Kazmi

Language: English

Topic: Advancements in PLL and VCO Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4404037888

FWCI: 0.779

Cites: 32

Cited by: 1

Related to: 10