Year: 2024
Type: article
Abstract: Memory management is necessary with the increasing number of multiconnected AI devices and data bandwidth issues. For this purpose, high-speed multiport memory is used. The traditional multiport memory solutions are hard-bounded to a fixed number of ports for read or write operations. In this letter, we proposed a pseudo-quad-port memory architecture. Here, ports can be configured (1-port, 2-port, 3-port, and 4-port) for all possible combinations of read/write operations for the 6T static random access memory (SRAM) memory array, which improves the speed and reduces the bandwidth for data transfer. The proposed architecture improves the bandwidth of data transfer by$4\times $. The architecture provides$1.3\times $and$2\times $area efficiency compared to dual-port 8T and quad-port 12T SRAM.
Source: IEEE Embedded Systems Letters
Institution: Indian Institute of Technology Indore
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W4404101847