Work

A Sub-Sampling 35GHz PLL in 45nm PDSOI BiCMOS with 37fs Integrated Jitter and a FoM of -252dB

Year: 2024

Type: conference-paper

Source: IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)

DOI: 10.1109/bcicts59662.2024.10745671

Authors: Christopher Chen, Yan Zhang, Hao-Yu Chien, Jiazhang Song, Jia Zhou, Chao-Jen Tien, Sudhakar Pamarti, Chih-Kong Ken Yang, Mau-Chung Frank Chang

Institution: University of California, Los Angeles

Language: English

Topic: Advancements in PLL and VCO Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

Funder: Air Force Research Laboratory

OpenAlex ID: W4404295264

FWCI:

Cites: 13

Cited by:

Related to: 10