Work

Single-Chip 30 GHz SiGe Sub-Sampling PLL with 28.3 fs Jitter

Year: 2024

Type: conference-paper

Source: IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)

DOI: 10.1109/bcicts59662.2024.10745698

Authors: Dimitre Dimitrov, Mark D. Hickle, Matthew Speir, Joseph M. Krzyzek, Daniel P. Lacroix, Shail Srinivas, Robert Sepanek, Spencer Desrochers, Steven Eugene Turner

Institution: BAE Systems (United States)

Language: English

Topic: Advancements in PLL and VCO Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4404295459

FWCI:

Cites: 11

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Related to: 10