Work

Spacer Design Strategies at Sub-5-nm Technology Node for Junctionless Forksheet FET: Bridging Device Optimization and Circuit Efficacy—A Dielectric Perspective

Year: 2024

Type: article

Source: IEEE Transactions on Dielectrics and Electrical Insulation

DOI: 10.1109/tdei.2024.3497877

Authors: Devika Gurre, Vinai Dasari, Kavya Mulaga, Sresta Valasa, Venkata Ramakrishna Kotha, Sunitha Bhukya, Praveen Kumar Mudidhe, Shubham Tayal, Bheemudu Vadthya, Narendar Vadthiya

Institutions: Maharaj Vijayaram Gajapathi Raj College of Engineering, National Institute of Technology Warangal, National Institute of Technology Delhi

Language: English

Topic: Advancements in Semiconductor Devices and Circuit Design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4404317259

FWCI: 1.65

Cites: 21

Cited by: 16

Related to: 10