Performance Evaluation of Adder Topologies Integrated into MAC Units and MLP Model for Digit Recognition
Year: 2024
Type: conference-paper
Authors: Ajay Sabareesh B, P.K. Moulya, Mohammed Aftab Hussain, Premananda B. S.
Institution: R.V. College of Engineering
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W4404349365