Work

Area and Power Optimized RTL to GDS II Flow of a Telecommunication Receiver Core

Year: 2024

Type: conference-paper

Source: International Conference on Circuits, Control, Communication and Computing (I4C)

DOI: 10.1109/i4c62240.2024.10748428

Authors: Jayasurya K., Ajith R., Premananda B.S.

Institution: R.V. College of Engineering

Language: English

Topic: VLSI and FPGA Design Techniques

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4404371306

FWCI: 1.612

Cites: 18

Cited by: 2

Related to: 10