Work

Time-to-Digital Converter Based Self-Timed Ring Oscillator: An FPGA Implementation

Year: 2024

Type: conference-paper

Abstract: This paper proposes an FPGA implementation of Self-Rimed Ring Oscillator (STRO) based Time-to-Digital Converter (TDC). Thanks to the STRO features, this TDC is able to achieve a time resolution as fine as needed by simply increasing its number of stages. Even if the achievable time resolution is close to the tenths of picoseconds, the approach does not require a high frequency oscillator. This resolution is only limited by the STRO-stage noise in the FPGA. As a hardware proof-of-concept, this TDC has been implemented in a Cyclone IV FPGA to further confirm and evaluate the advantages of our proposed TDC architecture. Most of the measurements are perfectly in accordance with our theoretical claims.

Source: IFIP/IEEE International Conference on Very Large Scale Integration

DOI: 10.1109/vlsi-soc62099.2024.10767784

Authors: Assia El-Hadbi, Oussama Elissati, Laurent Fesquet

Institutions: Institut National des Postes et Télécommunications, Institut polytechnique de Grenoble, Centre National de la Recherche Scientifique, Techniques of Informatics and Microelectronics for Integrated Systems Architecture

Language: English

Topic: Advancements in PLL and VCO Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: green

OpenAlex ID: W4404530229

FWCI: 0.799

Cites: 12

Cited by: 1

Related to: 10