Hardware/Software Runtime for GPSA Protection in RISC-V Embedded Cores
Year: 2025
Type: conference-paper
Abstract: State-of-the-art hardware countermeasures against fault attacks are based, among others, on control-flow and code integrity checking. Generalized Path Signature Analysis and Continuous Signature Monitoring can assert these integrity properties. However, supporting such mechanisms requires a dedicated compiler flow and does not support indirect jumps. This work proposes a technique based on a hardware/software runtime to generate those signatures while executing unmodified off-the-shelf RISC-V binaries. To the best of our knowledge, this is the first solution for providing this level of protection against fault injection on unmodified binaries. The proposed approach has been implemented on a pipelined processor, and experimental results show an average slowdown of ×3.35 and an area overhead of at least ×1.86 compared to unprotected implementations.
Authors: Louis Savary, Simon Rokicki, Steven Derrien
Institutions: Centre National de la Recherche Scientifique, Institut national de recherche en sciences et technologies du numérique, Institut de Recherche en Informatique et Systèmes Aléatoires, Centre Inria de l'Université de Rennes, Université de Rennes, Université de Bretagne Occidentale, Laboratoire des Sciences et Techniques de l’Information de la Communication et de la Connaissance
Language: English
Subfield: Artificial Intelligence
Field: Computer Science
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W4404531518