Year: 2024
Type: article
Abstract: Interference within a multi-core architecture may have several origins. Understanding where interference comes from is mandatory for verification and certification purposes. Unfortunately, the complexity of current architectures makes it difficult to quantify such interference. In this article, a new approach is introduced that enables benchmark configurations to isolate and quantify interference. An experiment with DMA interference is presented and shows a WCET overhead of up to 0.26% at 25 Mbit/s. This experiment was also able to discover and identify interference related to DMA, such as interruptive flow overhead, around 3% for 25 Mbit/s, or packet transmission memory access overhead, around 9% for 25 Mbit/s.
Source: ACM SIGAda Ada Letters
Institutions: Centre National de la Recherche Scientifique, Université de Bretagne Occidentale, Laboratoire des Sciences et Techniques de l’Information de la Communication et de la Connaissance, Université de Bretagne Occidentale, Observatoire de Paris, Laboratoire d’études spatiales et d’instrumentation en astrophysique, Centre National d'Études Spatiales
Language: English
Topic: Real-Time Systems Scheduling
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: bronze
OpenAlex ID: W4404533177