Work

Performance Projection of Gate-All-Around (GAA)-Based Negative Capacitance Complementary FET (NC-CFET) Relative to Standard CFET

Year: 2024

Type: article

Abstract: In this article, we have compared the negative capacitance complementary FET (NC-CFET) from a device-circuit perspective with the experimentally demonstrated CFET. NC-CFET could potentially offer additional advantages over conventional CFET, like enhancement in the sub-threshold behavior, reduction in threshold voltage variability, improvement in noise margin, low supply voltage, and high-speed operation, etc. The comparative study shows the improvement in the logic devices, as well as SRAM memory cell with the use of negative capacitance concept. Detailed circuit-level simulations have been used to analyze the performance gains with NC-CFET. Further, we have demonstrated multi layer NC-CFET with vertically stacked N/P channels for ON-current matching, symmetric inverter switching, and improved static noise margin (SNM) in SRAM.

Source: IEEE Journal of the Electron Devices Society

DOI: 10.1109/jeds.2024.3503283

Authors: Abhishek Kumar, Shruti Mehrotra, Anand Bulusu, Avirup Dasgupta

Institution: Indian Institute of Technology Roorkee

Language: English

Topic: Advancements in Semiconductor Devices and Circuit Design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: gold

Estimated APC paid: $1,350

Funder: Indian Institute of Technology Roorkee