Work

Design and Analysis of L3 Cache Embedded-GPU-High Bandwidth Memory Architecture with Reduced Energy and Latency for AI Computing

Year: 2024

Type: conference-paper

Source: IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)

DOI: 10.1109/epeps61853.2024.10753867

Authors: Haeseok Suh, Jiwon Yoon, Keeyoung Son, Seonguk Choi, Keunwoo Kim, Junghyun Lee, Taein Shin, Hyunjun An, Taesoo Kim, Jungmin Ahn, Hyunah Park, Hyunsik Kim, Taeil Bae, Haekang Jung, Joungho Kim

Institutions: Korea Advanced Institute of Science and Technology, SK Hynix (South Korea)

Language: English

Topic: 3D IC and TSV technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4404577358

FWCI: 5.642

Cites:

Cited by: 7

Related to: 10