Work

A 155 MHz Low-Jitter PLL for Enhanced Signal Integrity in High-Speed Interconnects

Year: 2024

Type: conference-paper

Source: IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)

DOI: 10.1109/epeps61853.2024.10754287

Authors: Mulat Ayinet Tiruye, Olani Baissa Gerba, T. Hui Teo

Institutions: University of Pisa, Singapore University of Technology and Design

Language: English

Topic: Advancements in PLL and VCO Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4404577441

FWCI:

Cites: 13

Cited by:

Related to: 10