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Single-Layer Wiring Design in UCIe to Realize Low-Cost Interposer Substrate

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Year: 2024
Type: conference-paper
Source: IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)
DOI: 10.1109/epeps61853.2024.10754582
Authors: Soshi Shimomura, Yutaka Uematsu, Katsuya Kikuchi, Haruo Shimamoto, Yuuki Araga, Shinichi Ouchi
Institution: National Institute of Advanced Industrial Science and Technology
Language: English

Topic: 3D IC and TSV technologies
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
SDG: Industry, innovation and infrastructure

Open Access status: closed

Funder: New Energy and Industrial Technology Development Organization
Award: G3098776136
OpenAlex ID: W4404577486
FWCI: 1.612
Cites: 2
Cited by: 2
Related to: 10
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