Work

A 16-kB 65-nm GC-eDRAM Macro With Internal Bias Voltage Generation Providing Over 100-μs Retention Time

Year: 2024

Type: article

Source: IEEE Journal of Solid-State Circuits

DOI: 10.1109/jssc.2024.3489793

Authors: Odem Harel, Andac Yigit, Eliana Feifel, Robert Giterman, Andreas Burg, Adam Teman

Institutions: Bar-Ilan University, École Polytechnique Fédérale de Lausanne

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

Funder: Council for Higher Education

OpenAlex ID: W4404628891

FWCI: 0.728

Cites: 30

Cited by: 7

Related to: 10