Insights Into Threshold Voltage Variability in Negative Capacitance Junctionless Transistor
Year: 2024
Type: article
Abstract: This work investigates the statistical variability of threshold voltage$(\sigma V_{\mathrm { th}})$and its sensitivity to critical geometrical parameters in negative capacitance (NC) junctionless (JL) and conventional JL transistors through quantum-corrected TCAD simulations. Threshold voltage variability$(\sigma V_{\mathrm { th}})$considering the statistical variation is assessed by varying the gate length, film thickness, channel doping, equivalent oxide thickness, and ferroelectric thickness. Results showcase$\sigma V_{\mathrm { th}}$owing to the process-induced variation in the device parameters can be reduced considerably by integrating the ferroelectric layer in the gate stack of JL devices. Among all the device parameters, variability analysis shows that$\sigma V_{\mathrm { th}}$degrades more against the variation in film, equivalent oxide, and ferroelectric thicknesses. As channel doping is critical to NCJL devices, we showcase that designing the NCJL transistors with moderate channel doping of 1018 cm-3 considerably lowers the$\sigma V_{\mathrm { th}}$against the device parameter variation. This work features the systematic methodology to lower the process-induced$V_{\mathrm { th}}$variability in NCJL devices while highlighting the potential significance of moderately doped channels at shorter technology nodes.
Authors: Ruma S. R., Vita-Pi Ho Hu, Manish Gupta
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: gold
Estimated APC paid: $1,350
Award: G8814241746
OpenAlex ID: W4404628907