Year: 2024
Type: conference-paper
Abstract: This paper presents GemIMC, a High Level Synthesis (HLS) based configurable digital unit architecture for accelerating Neural Networks (NN) at the edge using In Memory Computing (IMC). The proposed architecture is capable of supporting any type of memory technology, be it CMOS or resitive, with digital or analog storage capabilities. GemIMC aims to facilitate design space exploration among different IMC-related parameters and provide a top architecture for prototyping. By taking as input the IMC-tile parameters such as storage type (analog/digital), size, latency, power and process variability, GemIMC provides a an estimation of the full system's latency, area, and power consumption, taking into account the full digital control. The Tensorfiow-to-GemIMC environment flow allows for direct evaluation of the ineference accuracy for any type of NN, considering the variability associated with analog computation (when needed). The proposed work provides a flexible and efficient solution for IMC-based NN inference on the edge, along with a methodology for writing the IMC tile model to ensure compatibility with the top architecture.
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W4404681007