Work

Global Placement Exploiting Soft 2D Regularity

Year: 2024

Type: article

Abstract: Cell placement is a step of paramount importance in chip physical design and requests relentless effort for continuous improvement. Recently, designs with two-dimensional (2D) processing element arrays have become popular primarily due to their deep neural network hardware applications. The 2D array regularity is similar to but different from the regularity of conventional datapath designs. To exploit the 2D array regularity, this work develops a new global placement technique, Placement of Arrays with SOft Regularity (PASOR), built upon RePlAce, the state-of-the-art placement framework. Experimental results from various designs show that the proposed approach can reduce global routing wirelength by 11% and 6% compared to RePlAce and a previous work on datapath driven placement, respectively.

Source: ACM Transactions on Design Automation of Electronic Systems

DOI: 10.1145/3705729

Authors: Donghao Fang, Boyang Zhang, Hailiang Hu, Wuxi Li, Bo Yuan, Jiang Hu

Institutions: Texas A&M University, Rutgers, The State University of New Jersey, Advanced Micro Devices (United States)

Language: English

Topic: VLSI and FPGA Design Techniques

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: hybrid

OpenAlex ID: W4404699396

FWCI:

Cites: 30

Cited by:

Related to: 10