Flip-chip package solder-underfill reliability using finite element analysis
Year: 2024
Type: article
Abstract: A semiconductor package is responsible to safeguard the die from the external environment that can affect its performance and reliability. A flip-chip package ensures that the assembly, which is capable of high input-output function, maintains its operation and safeguards the interconnection paths particularly the solder ball deformation and fatigue. In this study, a finite element analysis model of the solder-underfill layers of a flip-chip package was developed and validated by statistical comparison of the warpage and stress from experimental data and theoretical calculations of composite deformation and stress. A quarter model was constructed, and proper boundary conditions and loads were applied. The results have shown statistical agreement with experimental measurements and the theoretical solution. After validation, the developed finite element analysis model was then used to perform a design of experiment on the solder-underfill layer of the package. The thermo-mechanical behaviors of the flip-chip package were then observed and analyzed for variations in the solder-underfill layer. The results have shown desirability of 0.8491 with an optimal layer thickness setting of 0.06 mm and solder content of 18.1% in consideration of the nonlinear factor effect of solder content on the die stress.
Source: Results in Engineering
Institution: De La Salle University
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: gold
Estimated APC paid: $1,490
OpenAlex ID: W4404768509