Work

A 97.8 GOPS/W FPGA-Based Residual-Block-Aware CNN Accelerator Featuring Multi-Clock PW 2 Pipeline and Adaptive-Resolution Quantization

Year: 2024

Type: article

Source: IEEE Transactions on Circuits and Systems I Regular Papers

DOI: 10.1109/tcsi.2024.3505299

Authors: Jixuan Li, Ke Li, Ka-Fai Un, Wei-Han Yu, Rui P. Martins, Pui-In Mak

Institution: University of Macau

Language: English

Topic: Advanced Neural Network Applications

Subfield: Computer Vision and Pattern Recognition

Field: Computer Science

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

Funders: VNU Science and Technology Development Fund, Universidade de Macau

Awards: G2299472110, G5378438400, G6548532224

OpenAlex ID: W4404787918

FWCI: 0.56

Cites: 37

Cited by: 4

Related to: 10