Work

Hierarchical Model Checking of SystemVerilog-Specified Asynchronous Circuits for Deadlock Detection

Year: 2024

Type: article

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI: 10.1109/tcad.2024.3509798

Authors: Longlong Lu, Minxue Pan, Yifei Lu, Xuandong Li

Institution: Nanjing University

Language: English

Topic: Formal Methods in Verification

Subfield: Computational Theory and Mathematics

Field: Computer Science

Domain: Physical Sciences

Open Access status: closed

Funder: National Natural Science Foundation of China

Award: G8404754680

OpenAlex ID: W4404847752

FWCI:

Cites: 33

Cited by:

Related to: 10