Work

IR-drop and Routing Congestion Aware PDN Refinement Framework for Timing Optimization

Year: 2024

Type: conference-paper

Source: International SoC Design Conference

DOI: 10.1109/isocc62682.2024.10762734

Authors: Yu-Guang Chen, Hung-Han Chang, Yu-Chuan Liang, Wen-Hsiang Chang, I-Ching Tsai, Chih-Wei Lin, Yun-Chih Chang, Mango Chia-Tso Chao

Institutions: National Central University, Realtek (Taiwan), National Yang Ming Chiao Tung University

Language: English

Topic: VLSI and FPGA Design Techniques

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4404848027

FWCI: 0.806

Cites: 7

Cited by: 1

Related to: 10