Year: 2024
Type: conference-paper
Abstract: This work provides a vision on how to tackle the underutilization of compute resources in FPGA SoC devices used across 5$G$and edge computing infrastructures. A first step towards this end is the implementation of a resource management layer able to migrate and scale functions in such devices, based on context events. This layer sets the basis to design a hierarchical data-driven micro-orchestrator in charge of providing the lifecycle management of functions in FPGA SoC devices. In the O-RAN context, the micro-orchestrator is foreseen to take the form of an xApp/rApp tandem trained with RAN traffic and context data.
Institution: Centre Tecnologic de Telecomunicacions de Catalunya
Language: English
Subfield: Computer Networks and Communications
Field: Computer Science
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W4404915938