12b 500MS/s successive‐approximation‐register‐assisted pipeline analogue‐to‐digital convertor using a four‐stage ring amplifier with coarse‐analogue‐to‐digital convertor embedded
Year: 2024
Type: article
Abstract: This article presents a 12b 500MS/s successive‐approximation‐register‐assisted pipeline analogue‐to‐digital converter. By adopting a new auto‐zero scheme, a calibration‐free four‐stage ring residue amplifier with a small offset cancellation capacitor is proposed. In addition, the coarse‐analogue‐to‐digital converter of the second stage is embedded into the amplification phase, which relaxes the comparison periods of the first and second stages by 25.0% and 17.4%, respectively. Post‐simulated in 28‐nm CMOS technology with a 0.9 V supply, the analogue‐to‐digital converter achieves 62.2 dB SNDR and 78.1 dB SFDR. It consumes 8.45 mW with an on‐chip reference voltage buffer, resulting in Schreier's figure of merit (FoM S ) of 166.9 dB.
Source: Electronics Letters
DOI: 10.1049/ell2.70101
Authors: Linghao Liu, Junyan Ren, Fan Ye
Institutions: Fudan University, State Key Laboratory of ASIC and System
Language: English
Subfield: Biomedical Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: gold
Estimated APC paid: $2,540
OpenAlex ID: W4405202191