Work

RIVL: A Low-Cost SoC Agile Development Platform for Multiple RISC-V Processors Design and Verification

Year: 2024

Type: article

Source: IEEE Transactions on Circuits and Systems I Regular Papers

DOI: 10.1109/tcsi.2024.3509634

Authors: Lida Xu, Zewen Cao, Hualong Zhao, Zhuo Peng, Yuchi Miao, Chunan Zhuang, Hongrui Ruan, Yuying Dong, Chuanbin Zeng, Bo Li, Jiajun Luo

Institutions: Chinese Academy of Sciences, Institute of Microelectronics, Institute of Computing Technology, Peng Cheng Laboratory

Language: English

Topic: Embedded Systems Design Techniques

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

Funder: Beijing Science and Technology Planning Project

Award: G4562036928

OpenAlex ID: W4405231458

FWCI: 0.641

Cites: 18

Cited by: 2

Related to: 10